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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
Once the EDIF netlist is generated, import the EDIF into the Project Navigator. The ispLEVER software automati-
cally detects the provided EDIF netlist of the instantiated IP core in the design. The step-by-step procedure pro-
vided below describes how to perform Place and Route in ispLEVER for an ORCA device:
1. Create a new working directory for Place and Route.
2. Start a new project, assign a project name and select the project type as EDIF.
3. Select the ORSPI4 (or ORSPII if that is the option available) target device, with -2 speed grade and the 1036
package.
4. Copy the following ?les to the Place and Route working directory:
a) eval\ngo\spi_324l_o4_1_001.ngo
b) eval\prf\exemplar qspi3_link.prf (with the LeonardoSpectrum EDIF)
eval\prf \synplicity\qspi3_link.prf (with the Synplify EDIF)
c) The top-level EDIF netlist generated from running synthesis (with Synplify or Leonardo)
5. Rename the qspi3_link.prf ?le (in step 4) to match the project name. For example, if the project name is
“demo”, then the .prf ?le must be renamed to demo.prf. The preference ?le name must match that of the project
name.
6. Import the EDIF netlist into the project.
7. In the ispLEVER Project Navigator, select Tools->Timing Checkpoint Options. The Timing Checkpoint Options
window will pop-up. In both Checkpoint Options, select Continue.
8. In the ispLEVER Project Navigator, highlight Place and Route Design, with a right mouse click select Proper-
ties. Set the following properties:
– Routing Passes: 10 for Synplify and LeonardoSpectrum EDIF
– Placement Iterations: 1
– Placement Save Best Run: 1
– Placement Iteration Start Point: 1
– Routing Resource Optimization: 0
– Routing Delay Reduction Passes: 1
– Placement Effort Level: 5
All other options remain at their default values.
9. Select the Place and Route Trace Report in the project navigator to execute Place and Route and generate a
timing report for ORCA.
10. Highlight Place and Route TRACE Report, with a right mouse click and select Force One Level. A new timing
report is generated.
Note that it is possible that timing results will change under different versions of synthesis tools or different releases
of ispLEVER. If this is the case, multiple placement iteration would need to be run to ?nd the one with 0 timing
errors. Multiple placement iterations are run by increasing the “Placement Iterations” value.
Reference Information
The SPI-3 LINK interfaces in the Quad SPI-3 to SPI-4 Bridge IP core solution are compliant with the standard OIF-
SPI3-01.0. A complete description of this standard is given in the speci?cation document.
? Optical Internetworking Forum (OIF). System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Phys-
ical and Link Layer Devices. OIF-SPI3-01.0.
A complete description of the SPI-4 standard is given in the speci?cation document
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